The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component or line that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs.
As one application, imaging sensors are incorporated in an integrated circuit. The existing imaging sensor has logic and pixel array on the same Si wafer and another wafer is a carrier only. Various issues may present in the existing imaging sensor structure. In one example, process tuning to image sensors impacts logic circuit area. In another example, small pixel layout suffers low quantum efficiency (QE) and full well capacity (FWC) due to devices occupancy. In yet another example, image signal processor (ISP) seizes a larger layout area, leading to low gross die count per unit area.
Therefore, what is needed is a structure for imaging sensor and method making the same to address the above issues.